In a complementary metal-oxide semiconductor (CMOS) circuit in partially depleted silicon on insulator (PD-SOI) technology, the delay is dependent on its switching history. When a circuit first switches after sitting idle for a few milliseconds (ms) or more it will have a longer or shorter delay than when it switches again within a few nanoseconds (ns). The first switch of the circuit is referred to herein as 1SW, while the second switch is referred herein as 2SW. If the same circuit is switching on a regular basis, every few ns or less, it will have a third delay characteristic of steady state operation, referred to herein as SS. These effects, known as SOI history, are required to be measured to accurately characterize the performance of PD-SOI circuits.
The measurement of SOI history requires input pulse widths of a few ns and picoseconds (ps) time resolution, see, for example, Ketchen et al., “Circuit and Technique for Characterizing Switching Delay History Effects in Silicon on Insulator Logic Gates,” Review of Scientific Instruments, Vol. 75 , pp. 768-771 , March 2004. Typically, such measurements have been made as bench tests on limited hardware using high speed probing techniques and equipment. These measurements are difficult to perform during processing in a manufacturing environment because of problems with noise, shielding and test time. Bench measurements have shown that the PD-SOI history is often 10-15% in present CMOS technology and it is a strong function of device design. History variation across a wafer may be in excess of 5%.
Recently an approach has been described for measuring SOI history using a self-calibrating, self-timed technique with dc signal inputs and outputs, see, for example, Ketchen et al., “High Speed Test Structures for In-Line Process Monitoring and Model Calibration,” Proc. 2005 IEEE International Conference on Microelectronic Test Structures , pp. 33-38 , April 2005. History measurements with resolution of 1% are achievable without the use of high frequency equipment. This design has been implemented and is now routinely used in a manufacturing environment to gather data for understanding the effects of process and statistical variations on history. This technique measures only the fractional difference between 1SW and 2SW delays. The question of where SS delay lies with respect to 1SW and 2SW delays is specifically not addressed with this structure, nor are the actual 1SW and 2SW delays themselves measured.
The technology is often evaluated in terms of the performance of one or more ring oscillators (ROs) which give SS delays. At present the offset between SS delays and 1SW and 2SW delays can only be obtained from time-resolved bench test measurements on appropriately designed and stimulated delay chain (DLC) structures. As an example, FIG. 1 is a diagram that illustrates the bench test data for an inverter chain experiment in 130 nanometer (nm) PD-SOI technology. Here the percentage delay differences for 1SW, 2SW and SS switching sequences represented as 1SW-SS, 2SW-SS, and 1SW-2SW histories are all plotted as a function of the power supply voltage VDD, where the nominal operating VDD=1.2V. The 1SW-2SW history peaks at around 1.1 V. It is noteworthy that at low VDD most of the history is associated with 2SW speedup compared to SS while at high VDD most of the history involves slowdown of 1SW with respect to SS. At VDD=1.2 V, SS delay, also measured with a RO, will be about 3.5% more than the average of 1SW and 2SW delays while at VDD=1.8V it will be 3.5% less.
Measuring only the 1SW-2SW history provides considerable insight in the delay variability, but also fails to correlate this history with SS delays. It is thus of considerable interest and value to develop a test structure that allows one to routinely measure as an inline test on a standard parametric tester the 1SW-SS and 2SW-SS histories as well.